1. Field of the Invention
The present invention relates to a microcomputer capable of entering a mode in which internal buses are divided into two buses, one bus between a CPU and a memory (called the memory bus hereunder), the other bus between the CPU and peripheral circuits (called the peripheral bus hereunder) so that the memory and the peripheral circuits may be tested without the intervention of the CPU (the mode is called the bus isolation mode hereunder).
2. Description of the Prior Art
FIG. 6 is a block diagram of a conventional microcomputer. In FIG. 6, reference numeral 61 is a microcomputer; 62 is a CPU of the microcomputer 61; 63 is a memory such as a ROM or a RAM built in the microcomputer 61; 64 is a body of peripheral circuits such as I/O and communication circuits incorporated in the microcomputer 61; 65 is a memory bus; 66 is a peripheral bus; and 67 is an external bus located outside the microcomputer 61.
Reference characters ISO and ISOB are control signals that are outputted by the CPU 62. The signal ISOB is an inverted signal of the control signal ISO. The control signals ISO and ISOB are supplied to appropriate circuit elements that need them via a control bus, not shown. The control signal ISO is driven High when the microcomputer 61 enters the bus isolation mode; the control signal ISOB is brought High when the microcomputer 61 operates in a mode other than the bus isolation mode.
Reference numeral 68a represents a transmission gate that comprises a P- and an N-channel transistor. The transmission gate 68a is turned on and off by the control signal ISO inputted to the gate of the P-channel transistor and by the control signal ISOD inputted to the gate of the N-channel transistor. The transmission gate 68a connects the CPU 62 with the peripheral bus 66.
Reference numeral 68b denotes another transmission gate that includes a P- and an N-channel transistor. The transmission gate 68b is also turned on and off by the control signal ISO inputted to the gate of the P-channel transistor and by the control signal ISOB inputted to the gate of the N-channel transistor. The transmission gate 68b connects the CPU 62 with the memory bus 65.
Reference numeral 68e stands for another transmission gate that includes a P- and an N-channel transistor. The transmission gate 68e is turned on and off by the control signal ISOB inputted to the gate of the P-channel transistor and by the control signal ISO inputted to the gate of the N-channel transistor. The transmission gate 68e connects the peripheral bus 66 with the external bus 67.
Reference numeral 68f is another transmission gate that includes a P- and an N-channel transistor. The transmission gate 68f is turned on and off by the control signal ISOB inputted to the gate of the P-channel transistor and by the control signal ISO inputted to the gate of the N-channel transistor. The transmission gate 68f connects the memory bus 65 with the peripheral bus 66.
In operation, when the microcomputer 61 is in a mode other than the bus isolation mode, the control signal ISO is driven Low and the control signal ISOB is brought High. These settings turn off the transmission gates 68e and 68f and turn on the transmission gates 68a and 68b. At this point, the peripheral bus 66 is disconnected from the external bus 67 and the memory bus 65 from the peripheral bus 66, while the CPU 62 is connected to the peripheral bus 66 as well as to the memory bus 65. In this configuration, the CPU 62 may gain access to the memory 63 through the memory bus 65 and to the peripheral circuits 64 through the peripheral bus 66.
When the microcomputer 61 enters the bus isolation mode, the control signal ISO is driven High and the control signal ISOB is brought Low. This turns on the transmission gates 68e and 68f and turns off the transmission gates 68a and 68b. At this point, the peripheral bus 66 is connected to the external bus 67 and the memory bus 65 to the peripheral bus 66, while the CPU 62 is disconnected from the peripheral bus 66 as well as from the memory bus 65. This configuration makes it possible to gain direct access to the memory 63 and peripheral circuits 64 from the external bus 67 via the memory bus 65 and peripheral bus 66.
With the conventional microcomputer 61 of the above structure in a mode other than the bus isolation mode, suppose that the CPU 62 accesses the peripheral circuits 64. In that case, the load on'the CPU 62 is constituted by the peripheral circuits 64 and by the additional capacity of only the peripheral bus 66. When the CPU 62 gains access to the memory 63, the load on the CPU 62 is constituted by the memory 63 plus the additional capacity of the memory bus 65 alone. When the microcomputer enters the bus isolation mode, on the other hand, the load on an entity attempting to access the memory 63 or peripheral circuits 64 alone from the external bus 67 is made up of not only the memory 63 or peripheral circuits 64 but also the additional capacities of both the memory bus 65 and the peripheral bus 66. As a result, the operation threshold frequency tested on and obtained from the memory 63 or peripheral circuits 64 in the bus isolation mode differs necessarily from the operation threshold frequency of the memory 63 or peripheral circuits 64 in a mode other than the bus isolation mode. This means that the test data about components of the microcomputer 61 such as the memory 63 and peripheral circuits 64, when tested and acquired in the bus isolation mode, turn out to be useless.